Polkadot JAM is built on the PVM ISA and it uses an entirely custom instruction set. Last week we announced PVM2, a re-imagination of the PVM ISA towards standard RISC-V.
Our exploration work showed the following: A custom instruction set like PVM is not necessary. We can get competitive performance with almost standard RISC-V. An in-house comparison between our older JAVM (legacy PVM ISA) implementation and the new JAVM (PVM2 ISA) implementation showed identical performance, and both of them are 2x faster than PolkaVM.
Previously we still had to define PVM2 with 4 hard divergences compared with RV64E (hence almost standard). Today we’re announcing another milestone for PVM2 – it’s not almost standard RISC-V anymore, but fully standard compliant RISC-V!
Specification, Xjar + EEI
For the full spec, you can read it here. Two things may be of particular interest to you:
- We define the memory map as a 2³²-fold alias of one 4 GiB main-memory region. Fully standard compliant EEI definition, and it keeps being fast.
- Basic block and gas metering is solved elegantly modeled after RISC-V’s standard control-flow integrity extensions (chapter 23).
Performance
The performance comparison you see on our initial announcement benchmark still apply. And yes, this is standard compliant RISC-V.
We have further made another ~10-20% improvements around our crypto benchmarks, but those newer results currently remain unpublished and subject to change.
Security
Being standard compliant has enormous advantages. In particular, we’re able to integrate Spike, RISC-V’s official testsuite and simulator. This directly gives us additional coverage. Technically, Spike can also be integrated into the legacy PVM ISA and PolkaVM through the transpiler, but in that case, it cannot be a full test, because transpiler to recompiler part remain untested, and only the recompiler part is executed on-chain.
A standard ISA that has undergone significant industry scrutiny also means that unlike PVM ISA, it’s less likely to have unexpected design issues.
Hardware
Being standard RISC-V also allows us to explore running on a real hardware. This is much harder (if not possible) to do on the legacy PVM ISA, as one generally cannot reuse an existing open source RISC-V CPU design.
In fact, one of our community member is already exploring this direction, for which you can join our Matrix room to learn more.
Trademark
RISC-V is a trademark of RISC-V International, and they’re pretty clear that only standard compliant implementations can refer themselves as “RISC-V”. Per their FAQ:
If an implementation was based on the RISC-V specification but includes modifications beyond this framework, then it cannot be referenced as RISC-V.
The RISC-V community historically quite dislikes non-conformant implementations. It’s contrary to RISC-V’s goal, and leads to unnecessary fragmentation. This is also partially the reason why for PVM2 / JAR Chain, we moved away from PVM and tried hard to see if it’s possible to be both standard compliant and performant. Our results showed that we can.
On the other hand, PolkaVM, being a non-conformant implementation, currently still advertises itself as:
PolkaVM is a general purpose user-level RISC-V based virtual machine.
We want to note that this is technically a trademark violation.

