I love the idea of starting to experiment with RISC-V! Thought about that myself some time ago. Curious to see how it goes.
Some food for thought: recently, I caught up with Luke Wagner, one of the guys behind the WebAssembly spec, and talked with him about the architecture, and of course, my question was, “why the stack machine architecture which is harder to translate to register machine architecture of a real CPU”. And I found his point quite logical.
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It doesn’t matter if the source abstract VM is a stack or register machine. As it never matches 1:1 to a real CPU architecture, a compiler must still convert the code to the SSA form and then do register allocation. At that point, the source architecture is lost anyway.
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If you want to do register allocation efficiently, you have to follow values’ live ranges to be able to optimize values’ distribution to registers. And the stack machine architecture is much more convenient here: when a value is pushed to the stack, its live range starts, and when it’s popped from the stack, its live range is unconditionally over. So you don’t have to keep an eye on when it dies, you just know when it dies. So it simplifies the compiler’s design.
But that’s just one of the possible angles of view to the problem. So now we have a RISC-V compiler experiment and a WASM transpiler experiment, and I’m really curious about where it’s going to take us 